This invention relates to an improved memory cell of a dynamic type and, in particular, an improved dynamic memory cell which is highly integrated.
The incessant advance of semiconductor memory devices permits the highest integration density to be attained in the memory cells of ROMs. For example, a dynamic RAM of 256 K bits has been reduced to practice. In the research stage, a dynamic RAM of a 1 M bit class is being reported. Also known is a CCC-structured dynamic RAM, a particular type of a dynamic RAM. A dynamic RAM of 1 M bit using the CCC-structured memory cells was reported at the ISSCC in 1984.
A memory cell of a CCC structure will now be explained below referring to FIG. 1.
In FIG. 1, holes are formed in a major surface portion of a P type semiconductor substrate 11 and a high concentration layer 13 of an N.sup.+ type is formed on the surface of the hole. A high concentration layer 15 of the N.sup.+ type, which acts as a source or a drain of a transistor, is formed in the major surface portion of the substrate such that it is located adjacent to the high concentration layer 13 of the N.sup.+ type. A high concentration layer 17 of an N.sup.+ type, which serves as a drain or a source, is formed in the major surface portion of the substrate such that it is located opposite to the high concentration layer 15. A P type region 19 between the N.sup.+ type regions 15 and 17 acts as a gate. The N.sup.+ type region 17 is formed integral with the drain or the source of an adjacent memory cell. A capacitor formation oxide film 21 is formed on the inner surface of the N.sup.+ layer 13.
A field oxide film 23 is formed between one capacitor formation hole and an adjacent capacitor formation hole, noting that the film 23 is so formed as to separate the one capacitor formation hole from the adjacent capacitor formation hole, that is, to separate one capacitor from an adjacent capacitor. A high concentration layer 37 of the P.sup.+ type is formed below the field oxide film 23 to prevent an inversion. A gate oxide film 25 and gate electrode 27 are formed in this order on the P type area 19. The hole is filled with a polycrystalline silicon to provide a polycrystalline silicon layer 29. The polycrystalline silicon layer 29 provides a capacitor electrode. An insulating oxide film 31 is formed on the surface of the resultant structure, i.e., on the polysilicon layer 29, gate electrode 27, etc. An aluminum interconnection layer 33 is formed on the oxide film 31 so that it is electrically in contact with the N.sup.+ layer 17. The aluminum interconnection layer 33 serves as a bit line. The capacitor is formed at an area indicated by C in FIG. 1 to constitute one portion of a memory cell.
A transistor constituting the major portion of the memory cell is formed at that area defined by a symbol TR in FIG. 1. In this CCC-structured memory cell, the capacitance of the capacitor can be increased without exerting any adverse influence over the size of the memory cell, by adjusting the depth of the hole.
In order to obtain such a memory cell with high integration density, the width of the field oxide film 23, bit line 33 and electrode 27, as well as the interval of these adjacent elements, must be made smaller. The minimum dimension of these elements is determined by the resolution of mask alignment in the manufacture of LSIs.
In order to further enhance the integration density of the memory cell, it is necessary to make the interval between one hole and the adjacent hole equal to the width of the field oxide film 23. Thus, these holes must be formed in a self-aligned fashion to the field oxide film 23 in an attempt to form these holes in close proximity. If any mask alignment is required, then it is necessary that such holes be formed on both the sides of the field oxide film 23 with a mask alignment allowance since the hole-to-hole interval cannot be decreased down to the width of the field oxide film.
Where the hole 35 is to be formed in a self-aligned fashion to the field oxide film 23 as shown in a partially enlarged cross-section in FIG. 2, the following drawbacks are encountered.
FIG. 2 is a view for explaining the neighborhood of the N.sup.+ type layer 13 with the unimportant portion omitted for clarity. The N.sup.+ type layer 13 becomes much thinner in the neighborhood of the field oxide film 23. When the hole is to be formed utilizing an RIE (Reactive Ion Etching) device, etc., radiation damage occurs to the N.sup.+ layer 13. Furthermore, an overhang occurs below the field oxide film 23. Upon the occurrence of these phenomena, a greater leakage current flows due to the presence of the capacitor in the memory cell, thus degenerating the storage characteristic of the memory cell. It has been impossible to decrease by much the thickness of the field oxide film 23, because a possible inversion may occur in the conductivity type of the surface portion of the semiconductor substrate.
The high integration density of the memory cell and the consequent narrowing of a capacitor-to-capacitor interval cause a larger leakage current to flow between the memory cells. In particular, the depletion layers of the capacitors extend below the field oxide film 23, tending to produce a punch-through phenomenon due to the coupling of the depletion region between the adjacent memory cells. When such punch-through phenomenon occurs, then an interference occurs between the adjacent memory cells, causing a possible destruction of storage data.